There can be advantages associated with the utilization of high-k gate dielectrics in various semiconductor constructions, including, for example, transistor devices and capacitor devices. High-k dielectrics are understood to be dielectric materials having a dielectric constant greater than that of silicon dioxide, and can include, for example, Ta2O5, Al2O3, and numerous other materials.
There has been some interest in attempting to integrate high-k dielectric materials into standard CMOS flow. However, such presents several difficulties when utilized in conjunction with the silicon gate electrodes typical of CMOS constructions. For instance, direct deposition of silicon (such as, for example, polycrystalline silicon) on high-k gate dielectric films typically results in a reaction layer at the interface of the silicon and the dielectric. The reaction layer can occur during the silicon deposition, and/or during subsequent high-temperature annealing of the silicon. The reaction layer generates an interfacial film, such as a silicate, between the silicon and the dielectric material. This interfacial layer reduces the effective dielectric constant of the dielectric stack, and thus limits the scalability of the dielectric. Further, the interfacial layer can be a source of charge trapping/fixed charge, due in part to metal-atom d states and charged atom defects. The charge trapping/fixed charge can be affected by post-gate annealing, and can result in uncontrollable shifts in a threshold voltage of a transistor device. In addition, the threshold voltage can shift due to boron diffusion from a p-type conductively doped silicon into a high-gate dielectric. Such threshold voltage shifts can be particularly significant and problematic for high thermal budget processing, such as, for example, memory cell processing. The boron diffusion through the dielectric can be a problem in spite of the thickness increase of the dielectric associated with utilization of a high permittivity film.
For the above-discussed reasons, it would be desirable to develop new methods for incorporating high-k dielectric materials into CMOS flow. Additionally, since high-k dielectric materials are utilized in other semiconductor constructions besides CMOS assemblies, it would be desirable if the methodologies could be applicable to other semiconductor fabrication besides CMOS flow, and particularly if the methodologies could be applicable to capacitor device fabrication. Also, it would be desirable if the methodologies could be applied not only to high-k dielectric materials, but also to other dielectric materials.